Special Section on Selected Papers from the 9th Karuizawa Workshop Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits

In this paper, we discuss on accuracy of power dissipation models for CMOS VLSI circuits. Some researchers have proposed several e cient power estimation methods for CMOS circuits [1][2][3][4]. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-level etc., we have been (i) Measuring power consumption of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block. key words: CMOS VLSI circuits, low power design, power estimation